Memory devices, whether volatile or non-volatile, may be designed to operate over a wide range of operating frequencies, typically indicated to the memory devices by a host clock signal. For example, a single DRAM module may be designed to operate at any one of a number of frequencies between 800 MHz and 4000 MHz. While it can be desirable to optimize a memory module to operate at particular frequency, optimizations for one operating frequency may cause performance degradations at other operating frequencies. Accordingly, it would be beneficial to provide a method for optimizing memory devices to operate at multiple different frequencies, and memory devices capable of such optimization.